The present invention generally relates to semiconductor devices and more particularly to a protection circuit for use in semiconductor integrated circuits for protecting the same from voltage surge of input signals.
Recent semiconductor integrated circuits, particularly semiconductor memory devices such as SRAMs (static random access memory) or DRAMs (dynamic random access memory), have extremely fine patterned structures for increased integration density. Thus, such semiconductor integrated circuits are generally vulnerable to surge of electric input signals caused as a result of electrostatic discharge, and the like. When such a surge is applied, minute p-n junctions or capacitors in the integrated circuit easily cause breakdown.
In order to avoid such a breakdown of the essential part of the integrated circuit, currently used integrated circuits generally use a protection circuit between a bonding pad provided on the surface of a semiconductor chip, in which the integrated circuit is formed, and the input/output circuit of the integrated circuit, such that the voltage surge caused in the electric signals as a result of electrostatic discharge and the like, is dissipated immediately to the semiconductor substrate.
FIG. 1 shows an example of a conventionally used input protection circuit provided to an input stage of an integrated circuit.
Referring to FIG. 1, there is formed an input pad 1 on the surface of a semiconductor chip that constitutes a part of the integrated circuit, for achieving a connection to external circuits. Further, a conductor pattern 3, typically formed of aluminum or aluminum alloy, extends from the input pad 1 to a first stage circuit 2 of the integrated circuit designated as IC.
In the construction of FIG. 1, it will be noted that the conductor pattern 3 is connected to an N-channel MOS transistor T.sub.1 that has a gate connected to the ground. Thus, the transistor T.sub.1 is normally turned off. Only when a voltage surge is applied, the transistor T.sub.1 turns on and the electric charges on the conductor pattern 3 are dissipated to the ground. In the normal operational state where no voltage surge is applied, it should be noted that the electric signal supplied to the input pad 1 is further supplied to a diffusion region forming the source of the transistor T.sub.1 via the conductor pattern 3 and is supplied further to the first stage circuit 2 of the integrated circuit via a different conductor pattern of polysilicon. In FIG. 1, it should be noted that the resistance of the diffusion region is designated as R.sub.1 and the resistance of the polysilicon pattern is designated as R.sub.2.
When a large positive voltage is applied to the input pad 1 as a result of the voltage surge, on the other hand, the transistor T.sub.1 causes a breakdown between the source and drain thereof, and the electric charges on the conductor pattern 3 are dissipated to the ground. Further, when a large negative voltage exceeding the threshold voltage of the transistor T.sub.1 is applied to the input pad 1, the transistor T.sub.1 also causes a conduction and the electric charges on the conductor pattern 3 are dissipated to the ground. Thus, the transistor T.sub.1 and the resistances R.sub.1 and R.sub.2 form an input protection circuit 4 that clamps the voltage supplied to the circuit 2.
FIG. 2 shows the layout of the input protection circuit 4 of FIG. 1 provided on a semiconductor chip in a plan view. It should be noted that the illustrated example corresponds to the one disclosed in the Japanese Laid-open Patent Publication 3-209759, and is formed on a silicon substrate covered by an insulation film such as silicon oxide.
Referring to FIG. 2, the input protection circuit 4 includes an aluminum pattern 11 formed on a silicon oxide film provided on a silicon substrate. The aluminum pattern 11 corresponds to the conductor pattern 3 of FIG. 1 and is connected to an input pad (not shown) on the substrate. As will be understood from the plan view of FIG. 2, the aluminum pattern 11 has a comb-shaped form and includes fingers 11a-11c, wherein the fingers 11a-11c are connected electrically to an n-type diffusion region 13 formed in the silicon substrate by way of a plurality of contact holes 12 in the silicon oxide film. It should be noted that the diffusion region 13 forms the foregoing resistance R.sub.1 of FIG. 1. Further, another aluminum conductor pattern 14 extends from the other end of the diffusion region 13 to the first stage input circuit 2 of the integrated circuit IC. Thereby, a polysilicon pattern (not illustrated) may be interposed between the aluminum conductor pattern 14 and the integrated circuit as the foregoing resistance R.sub.2.
Further, there is provided another aluminum pattern 16 on the silicon oxide film on the silicon substrate such that the aluminum pattern has a comb-shaped form corresponding to the comb-shaped form of the aluminum pattern 11, wherein the aluminum pattern 16 is connected to the foregoing diffusion region 13 in the silicon substrate at contact holes 17 formed in the foregoing silicon oxide film on the semiconductor substrate. It should be noted that the aluminum pattern 16 is grounded and includes fingers 16a and 16b, such that the finger 16a extends between the fingers 11a and 11b of the pattern 11 with a generally uniform separation therefrom. Similarly, the finger 16b extends between the fingers 11b and 11c of the pattern 11, with a generally uniform separation. As a result, gaps g.sub.1 -g.sub.5 are formed between the pattern 11 and the pattern 16 as indicated in FIG. 2, with a generally uniform width for each of the gaps g.sub.1 -g.sub.5.
Further, a polysilicon pattern 18 including elongate fingers 18a-18e is provided underneath the silicon oxide film and hence below the level of the patterns 11 and 16 in electrical connection to the pattern 16 via contact holes 19 provided on the silicon oxide film, wherein the polysilicon pattern is disposed such that the fingers 18a-18e extend over the gaps g.sub.1 -g.sub.5 respectively. The polysilicon pattern 18 is isolated from the underlying silicon substrate by means of another thin silicon oxide film, and there are formed a plurality of transistors T.sub.1 having respective gates corresponding to the fingers 18a-18e of the polysilicon pattern 18, such that each of the transistors has a source corresponding to a part of the diffusion region 13 immediately below the contact hole 12 and a drain corresponding to a part of the diffusion region 13 immediately below the contact hole 17. It should be noted that the transistors T.sub.1 thus formed include respective gates connected to corresponding drains by way of the contact holes 19, while the respective drains are connected to the ground via the contact holes 17 and the patterns 16.
FIG. 3 shows the operation of the input protection circuit having the layout of FIG. 2.
Referring to FIG. 3, electrons (or holes) corresponding to the input signal applied to the input pad 1 are caused to flow to the input stage circuit 2 of the integrated circuit IC via the conductor pattern 11, the diffusion region 13, and the conductor pattern 14. Thereby, the electrons are dissipated to the ground when the transistors T.sub.1 formed in corresponding to the foregoing gaps g.sub.1 -g.sub.5 cause a conduction as a result of voltage surge applied to the input pad 11.
In the illustrated layout of FIG. 2, however, there arises a problem in that majority of the electrons supplied from the input pad 1 flow to the conductor pattern 14 via the branch 11a, while little electrons flow to other branches 11b and 11c. Thus, when the transistors T.sub.1 cause a conduction as a result of voltage surge, the electrons are dissipated to the ground preferentially through only one of the transistors T.sub.1 that corresponds to the foregoing gap g.sub.1, even though the transistors T.sub.1 are formed in correspondence to all of the gaps g.sub.1 -g.sub.5 and hence have a large current-carrying capacity. Thus, the conventional integrated circuit that uses the input protection circuit 4 of FIG. 2 has suffered from unsatisfactory surge suppression and risk of the integrated being damaged as a result of the voltage surge.